Bio.: Luca Benini holds the chair of digital Circuits and systems at ETHZ and is Full Professor at the Università di Bologna. He received a PhD from Stanford University. His research interests are in energy-​efficient parallel computing systems, smart sensing micro-​systems and machine learning hardware. He is a Fellow of the IEEE, of the ACM, a member of the Academia Europaea and of the Italian Academy of Engineering and Technology. He is the recipient of several awards including the 2023 IEEE CS E.J. McCluskey Award, and the 2024 IEEE CS Open Source Hardware contribution Award.

Bio.: Prof Yeo Yee Chia is currently the Deputy Chief Executive (Innovation & Enterprise), A*STAR. He provides strategic leadership and oversight of the Innovation & Enterprise Group and National Platforms. He orchestrates A*STAR's industry approach and priorities to ensure that A*STAR's translational activities achieve significant national impact and outcomes.
Prior to this, he was Assistant Chief Executive (Innovation & Enterprise), where he strengthened A*STAR's industry partnerships and commercialisation efforts. Prof Yeo also held various leadership roles in A*STAR, including Executive Director (IP Management) and Executive Director of the Science & Engineering Research Council (SERC). He leads substantial research efforts at A*STAR's Institute of Microelectronics, working on frontier microelectronic devices and key challenges in semiconductor technology. He plays a significant role in Singapore's Future of Microelectronics initiative to steer next-generation microelectronics strategy.
Prof Yeo is a renowned scholar in academia and a technology leader in the semiconductor industry, with expertise in transistor architecture, device modelling and simulation, materials, tools and processing technologies.
He spent 10 years at Taiwan Semiconductor Manufacturing Company (TSMC). He was Director of Research and Development (R&D) at TSMC where he led organisations spanning research, pathfinding, and development. He co-developed TSMC's industry-leading 7 nm, 5 nm, and 3 nm technologies, which has impacted the world in areas such as high performance computing, artificial intelligence, and consumer electronics.
In academia, he is Professor of Electrical and Computer Engineering, National University of Singapore (NUS), where he was an award-winning, high impact researcher with an outstanding track record of achievements. He published over 700 research papers and is an inventor of 289 US patents. 44 PhD students graduated under his tutelage.
He received his PhD and MS degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley, and MEng and BEng degrees in Electrical Engineering from NUS.

Bio.: Subramani (Subi) Kengeri is the Corporate Vice President and General Manager at Applied Materials, leading the Systems-to-Materials group since joining in 2020. He has led world-wide teams in technical and executive roles at Globalfoundries, TSMC, and Texas Instruments. He holds over 50 U.S. patents, and has delivered more than 100 invited talks and interviews.

Bio.: Professor Kiat Seng YEO, (PhD, PPA, PBS, FSAEng, FSNAS, FCAE, FIEEE, FAAET, FAIIA, FAAIA) received his BEng and PhD degrees in EE from Nanyang Technological University (NTU), Singapore. He has 37 years of experience in industry, academia, start-ups and consultancy. Currently, he is Advisor for Global Partnerships (President’s Office) and Director for Innovation and Enterprise (China) at the Singapore University of Technology and Design (SUTD) and Distinguished Professor at Tianjin University. Prof. Yeo is a widely known authority in low-power RF/mm-wave IC design and a recognized expert in CMOS technology. He was the Founding Chairman of the University Research Board, Founding Chairman of the Board of Graduate Studies, Member of the Academic Council, Associate Provost for Research, Founding Associate Provost for Graduate Studies, and Founding Associate Provost for International Relations at SUTD. Before his appointment at SUTD, he was Associate Chair (Research), Head of the Division of Circuits and Systems, and Founding Director of VIRTUS of the School of Electrical and Electronic Engineering at NTU. He has secured over S$70M of research grants as PI, published 14 books (4 Amazon Best Sellers), 7 book chapters, 700+ journal and conference papers, and holds 55 patents (27 US patents). Professor Yeo holds/held key positions in many international conferences as Advisor, General Chair and Technical Chair. He is one of the 7 “double academicians” of the Singapore Academy of Engineering and the Singapore National Academy of Science. He is also a Foreign Fellow of the Canadian Academy of Engineering and Fellows of the ASEAN Academy of Engineering and Technology, the Asia-Pacific Artificial Intelligence Association, the International Artificial Intelligence Industry Alliance, and the IEEE. He received 2 National Day Awards from the President of Singapore in 2009 and 2020 and awarded the Nanyang Alumni Achievement Award by NTU in 2009. He is the principal author of Integrated Circuit Design Research Ranking for Worldwide Universities 2008 and World University Research Rankings (WURR) 2020. Professor Yeo was recognized among the Top 2% Scientists Worldwide by Stanford University from 2020 to 2025, World’s AI Top Scientist by the International Artificial Intelligence Industry Alliance in 2023, and Top Scholar by ScholarGPS from 2023 to 2025.

Bio.: Don Chan is the vice president of R&D at Cadence Design Systems. He received his MS degree in electrical engineering from Santa Clara University in 1990. From 1986-1989, he was developing SPICE models. From 1989-1992, he was as ASIC Design Engineer at Fujitsu Microelectronics. From 1993-2018, Don held various leadership positions in both applications engineering and R&D at Synopsys. From 2018-present, Don is the VP of R&D collaborating with the world’s #1 foundry in developing the most advanced nodes. In addition, Don is also the product owner for the frontend products at Cadence which includes Conformal, Modus and Stratus. Don has given many keynote speeches in many conferences in Asia. Don is also currently a Lecturer at Santa Clara University.

Bio.: Keshab K. Parhi received the B.Tech. degree from the Indian Institute of Technology (IIT), Kharagpur, in 1982, the M.S.E.E. degree from the University of Pennsylvania, Philadelphia, in 1984, and the Ph.D. degree from the University of California, Berkeley, in 1988. He has been with the University of Minnesota, Minneapolis, since 1988, where he is currently the Erwin A. Kelen Chair and a Distinguished McKnight University Professor in the Department of Electrical and Computer Engineering.
He has published over 750 papers, is the inventor of 36 patents, and has authored the textbook VLSI Digital Signal Processing Systems: Design and Implementation (Wiley, 1999). His current research addresses VLSI architecture design of artificial intelligence and machine learning systems, signal processing systems, hardware security, quantum information science, and data-driven neuroengineering and neuroscience with applications to neuro-psychiatric disorders.
Dr. Parhi is the recipient of numerous awards including the 2003 EEE Kiyo Tomiyasu Technical Field Award; and the 2017 Mac Van Valkenburg award, and the 2012 Charles A. Desoer Technical Achievement award, from the IEEE Circuits and Systems Society. He served as the Editor-in-Chief of the IEEE Trans. Circuits and Systems, Part-I during 2004 and 2005, and currently serves as the Editor-in-Chief of the IEEE Circuits and Systems Magazine. He is a Life Fellow of IEEE, a Fellow of the American Association for the Advancement of Science (AAAS), the Association for Computing Machinery (ACM), the American Institute of Medical and Biological Engineering (AIMBE), and the National Academy of Inventors (NAI).

Bio.: Prof. Krishnendu Chakrabarty is the Fulton Professor of Microelectronics in the School of Electrical, Computer and Energy Engineering at Arizona State University (ASU). He is also the CTO of the SWAP Hub for the Department of War Microelectronics Commons (https://microelectronics.asu.edu/southwest-advanced-prototyping-hub/), and Director of the ASU Center for Semiconductor Microelectronics (ACME, http://acme.asu.edu). Before moving to ASU, he was the John Cocke Distinguished Professor and Chair of Electrical and Computer Engineering at Duke University. Prof. Chakrabarty is a recipient of the Humboldt Research Award from the Alexander von Humboldt Foundation, Germany, the IEEE Transactions on CAD Donald O. Pederson Best Paper Award, the IEEE Transactions on VLSI Systems Prize Paper Award, the ACM Transactions on Design Automation of Electronic Systems Best Paper Award, and over a dozen best paper awards at major conferences. He is also a recipient of the IEEE Computer Society Technical Achievement Award, the IEEE Circuits and Systems (CAS) Society Charles A. Desoer Technical Achievement Award, the IEEE CAS Society Vitold Belevitch Award, the Semiconductor Research Corporation (SRC) Technical Excellence Award, the SRC Aristotle Award, the SRC Innovation Award, the IEEE-HKN Asad M. Madni Outstanding Technical Achievement and Excellence Award, and the IEEE Test Technology Technical Council Bob Madge Innovation Award. He is a Research Ambassador of the University of Bremen (Germany) and he was a Hans Fischer Senior Fellow at the Institute for Advanced Study, Technical University of Munich, Germany during 2016-2019. He is a 2018 recipient of the Japan Society for the Promotion of Science (JSPS) Invitational Fellowship in the “Short Term S: Nobel Prize Level” category. He is also a recipient of the Distinguished Alumnus Award from the Indian Institute of Technology, Kharagpur. Prof. Chakrabarty is a Fellow of ACM, IEEE, and AAAS, and a Golden Core Member of the IEEE Computer Society. He is a Fellow of the National Academy of Inventors.

Bio.: Massimo Alioto is Provost's Chair Professor at the ECE Department of the National University of Singapore, where he leads the Green IC group, the Integrated Circuits and Embedded Systems area, and the FD-fAbrICS center on intelligent&connected systems. Previously, he held positions at the University of Siena, Intel Labs - CRL (2013), University of Michigan - Ann Arbor (2011-2012), University of California - Berkeley (2009-2011), EPFL - Lausanne.
He is (co)author of 400 publications on journals and conference proceedings, and four books with Springer (with two more coming). His primary research interests include ultra-low power and self-powered systems, green computing, circuits for machine intelligence, hardware security, and emerging technologies.
He was the Editor in Chief of the IEEE Transactions on VLSI Systems and Deputy Editor in Chief of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems. He was the Chair of the Distinguished Lecturer Program for the IEEE CAS Society, and was a Distinguished Lecturer for the SSC and CAS Society. Previously, Prof. Alioto was the Chair of the “VLSI Systems and Applications” Technical Committee of the IEEE Circuits and Systems Society (2010-2012). He served as Guest Editor of numerous journal special issues (JSSC, TCAS-I, JETCAS…), Technical Program Chair of several IEEE conferences (ISCAS, SOCC, PRIME, ICECS), and TPC member (ISSCC, ASSCC). His research group contribution has been recognized through various best paper awards (e.g., ISSCC), and in the ten technological highlights of the TSMC annual report, among the others. Prof. Alioto is an IEEE Fellow.

Bio.: Atsushi TAKAHASHI received his B.E., M.E., and D.E. degrees in electrical and electronic engineering from Tokyo Institute of Technology, Tokyo, Japan, in 1989, 1991, and 1996, respectively. He had been with the Tokyo Tech as a Research Associate from 1991 to 1997, and as an Associate Professor from 1997 to 2009 and from 2012 to 2015, and as a Professor from 2015. He had been with the Osaka University as an Associate Professor from 2009 to 2012. He is currently a Professor with Department of Information and Communications Engineering, School of Engineering, Tokyo Institute of Technology. He served as the TPC Chair of ASP-DAC 2018, the General Chair of ASP-DAC 2023, and he is currently a vice chair of Steering Committee of ASP-DAC. He also served as the chair/co-chair/TPC member of top conferences such as ASP-DAC, ISPD, ICCAD, DATE and VLSI-DAT. He was a Board of Governors of IEEE CASS from 2015 to 2019, the chair of All Japan Joint Chapter of IEEE CEDA from 2015 to 2016, the chair of Japan Joint Chapter of IEEE CASS from 2020 to 2021, and the President of Engineering Sciences Society of IEICE in 2021. His research interests include in VLSI layout design and combinational algorithms. He is a fellow of IEICE, and a senior member of IEEE and IPSJ, and a member of ACM.

Bio.: Hans-Joachim Wunderlich is a professor emeritus of the University of Stuttgart and Life Fellow of IEEE. He received his diploma degree in mathematics from the University of Freiburg, Germany, in 1981 and his Dr. rer. nat. (Ph.D.) from the University of Karlsruhe in 1986. Since 1991, he has been a full professor. From 2002 to 2018, he served as the director of the Institute of Computer Architecture and Computer Engineering at the University of Stuttgart, Germany. He has been an associate editor for various international journals and involved in the organization of a variety of IEEE conferences on the design, testing, and fault tolerance of electronic systems. He has published 17 books and book chapters and more than 330 reviewed scientific papers in journals and conferences. His research interests include testing, reliability, fault tolerance, and design automation of microelectronic systems.

Bio.: Puneet Gupta received the B.Tech. degree in electrical engineering from the Indian Institute of Technology Delhi, New Delhi, India, in 2000, and the Ph.D. degree from the University of California at San Diego, San Diego, CA, USA, in 2007. He is currently a Faculty Member with the Electrical and Computer Engineering Department, University of California at Los Angeles. He Co-Founded Blaze DFM Inc., Sunnyvale, CA, USA, in 2004 and served as its Product Architect until 2007. He has authored over 200 papers, 18 U.S. patents, a book and two book chapters in the areas of design-technology co-optimization as well as variability/reliability aware architectures. Dr. Gupta is an IEEE Fellow and was a recipient of the NSF CAREER Award, the ACM/SIGDA Outstanding New Faculty Award, SRC Inventor Recognition Award, and the IBM Faculty Award. He has led the multi-university IMPACT+ Center which focused on future semiconductor technologies. He currently leads the System Benchmarking theme within the SRC CHIMES JUMP 2.0 center.