Special Sessions

ISEDA 2025 Special Sessions


More special sessions will be updated...

Special Session 01

CEDA-adjoint special session: Deep Learning Inspired Algorithms for Physical Modeling and Analysis of Advanced IC Design

Organizer/Chair(s):

Yuanqing Cheng, Beihang University, China
Wenjian Yu, Tsinghua University, China


Invited Talks:
"Deep Learning Inspired Thermal-aware Modeling and Optimization for Chiplet Systems"

Yibo Lin (Peking University)

"G-SpNN: GPU-Accelerated Passivity Enforcement for S-Parameter Macromodeling with Neural Networks"

Zhou Jin (Zhejiang University)

"Machine Learning for Multi-corner Timing Analysis"

Yuanqing Cheng (Beihang University)

"Pre-layout Prediction of Parasitic Parameters in AMS Circuits Based on Graph Neural Networks"

Shan Shen (Nanjing University of Science and Technology), Wenjian Yu (Tsinghua University)

Special Session 02

Bridging AI and Hardware: Advancing Specialized Circuits, Design Automation, and Manufacturing

Motivation: Advances in semiconductor design and manufacturing are being driven by a convergence of artificial intelligence (AI) and novel hardware techniques, fueling unprecedented efficiency and innovation. Bridging the gap among chip manufacturing, edge deployment, and circuit design optimization has become essential for tackling the rising complexity and scalability demands of today’s systems. As technology node shrinks and application proliferates, balancing performance, cost, and reliability requires cross-layer solutions from fabrication to system-level automation.
This two-hour special session features four invited talks addressing these cross-cutting challenges. It begins with the design of a flexibly configurable, high-performance random number source specifically tailored for stochastic computing, highlighting crucial advancements in circuit design and configurability for new-generation AI hardware. The second talk presents a roadmap for design automation with machine learning, envisioning methodology advancements from supervised learning to foundation models targeting semi- and non-supervised learning scenarios. The third talk explores how large language model (LLM)-based foundation models revolutionize hardware design automation, reducing manual intervention in complex workflows and enabling efficient logic optimization, RTL synthesis, and layout generation. Finally, the session concludes with the deployment of edge-optimized LLMs for real-time anomaly detection in chip manufacturing, addressing latency, privacy constraints, and model adaptability in dynamic production environments.
Together, these presentations highlight how innovative tools and methodologies are revolutionizing both the development and deployment of semiconductor technologies. By fostering synergies across manufacturing intelligence, edge computing, and design automation, this session aims to inspire researchers and practitioners to reimagine chip design and manufacturing, and accelerate the development of scalable, robust, and high-performance semiconductor solutions.


Organizer/Chair(s):

Weikang Qian, Shanghai Jiao Tong University, China
Zheyu Yan, Zhejiang University, China


Invited Talks:
"Accuracy Analysis and Design Optimization for Low-Cost High-Accuracy Stochastic Circuit"

Kuncai Zhong (Hunan University)

"AI-Assisted EDA: from Supervised Learning to Circuit Foundation Models"

Zhiyao Xie ( Hong Kong University of Science and Technology)

" LLM for Hardware Design: Accelerating Automation with Large Language Models"

Zhenge Jia (Shandong University)

"Deploying Edge LLMs for Wafer Defect Detection in Chip Manufacturing"

Zheyu Yan (Zhejiang University)