EDA² | ISEDA 2025 | Technical Session

RTL and Gate-Level Simulation and Verification

Session Chair: Hongce Zhang, The Hong Kong University of Science and Technology (Guangzhou)

Abstract: The advancement of functional safety has made RTL-level fault simulation increasingly important to achieve iterative efficiency in the early stages of design and to ensure compliance with functional safety standards. In this paper, we extend IVerilog to support batch RTL fault simulation and integrate the event-driven algorithm and the concurrent fault simulation algorithm. Comparative experiments with a state-of-the-art commercial simulator and an open-source RTL fault simulator demonstrate that our simulator achieves a performance improvement of 2.2× and 3.4×, respectively.

Abstract: \emph{Combinational Equivalence Checking} (CEC) is essential for circuit verification, but traditional heuristic-based sweeping engine selection often results in inefficiencies. To address this, we enhance the previous Hybrid-CEC method by integrating proposed BDD sweeping, which significantly improves performance for circuits with high XOR chain density, achieving a 13.27$\times$ speed-up over Kissat solver. To address the lack of effective guidance for solvers in different verification scenarios, we propose the \emph{Auto-CEC} framework. This intelligent framework leverages DeepGate2 embeddings and a \emph{convolutional neural network} (CNN)-based classifier to dynamically predict the most suitable sweeping engine. Experimental results on industrial benchmarks demonstrate that Auto-CEC effectively balances accuracy and efficiency, achieving speed-ups of 6.02$\times$ to 11.29$\times$ over existing approaches.

Abstract: Combinational logic loops present critical design challenges by inducing signal contention and sustained oscillations, leading to excessive power dissipation and functional anomalies in integrated circuits. Prior methods have primarily focused on full condition generation for potential oscillations. However, these methods come with exponential complexity (O(2^n)) and often overlook the efficiency that can be gained by directly detecting oscillations, causing inefficient resource utilization. In this work, we propose OSCC-SA, an open-source static analysis framework directly detecting oscillatory behaviour in Strongly Connected Components (SCCs), the fundamental topological manifestation of combinational loops. We develop an enhanced SCC benchmark generation methodology building upon the 2024 Integrated Circuit EDA Elite Challenge dataset, incorporating comprehensive complexity metrics. Our experimental results demonstrate that the proposed loop-based reverse search algorithm achieves linear-time complexity (O(n)) across all benchmarks while maintaining 100% detection accuracy. The practical efficacy of OSCC-SA has been recognized with the first-class award at the Challenge.

Abstract: With the explosive growth in the complexity of integrated circuit designs, hardware emulation platforms face significant challenges in simulating designs with billions of gates using a single Field-programmable Gate Array (FPGA). This paper proposes a two-phase optimization framework: first, an initial hypergraph partitioning is performed using an improved FM algorithm, followed by the application of a targeted logic replication strategyv that consider the cost-effectiveness of replication on the partitioned results. By adopting the two-stage optimization strategy, our method maintains algorithmic efficiency while reducing computational complexity. Experimental results demonstrate that, compared to non-replication strategies, our approach achieves an average reduction of 17% in total hop distance while completing logic replication in a significantly shorter time, validating the effectiveness of phased optimization strategy.