A Statistical Static Timing Analysis Algorithm Based On Graph Neural Network
Presenter: Yufan Chen, Southeast University
Abstract: Satistical static timing analysis (SSTA) struggles with nonlinear MAX operations, which is crucial in block based statistical timing analysis. Most existing methods either incur high computational costs or rely on inaccurate approximations. In this work, we propose a SSTA algorithm based on graph neural network (GNN) to deal with non-Gaussian while balancing speed by using its node regression function. GNN eliminate the traversal propagation through message passing mechanisms and can simulate the nonlinear behavior of MAX operation through its attention mechanisms. Experimental results demonstrate that our model outperforms the First-order delay model and Skew-normal delay model in terms of accuracy, especially when skewness has a significant impact, while its time overhead is on the same order of magnitude as First-order model. Taking into account both accuracy and runtime, our proposed model has significant computational efficiency advantages while ensuring high prediction accuracy.
Pre-Routing Timing Estimation Considering Power Delivery Network
Presenter: Mingwei He, Southeast University
Abstract: In recent years, the demand for fast and accurate pre-routing timing prediction is increasing. However, existing machine learning (ML)-based methods for predicting pre-routing timing often overlook the impact of power delivery networks (PDNs), which are critical to IR drop and routing congestion, limiting the effectiveness of these approaches in real-world circuit designs. To address this challenge, we propose a multi-modal model that integrates PDN, layout, and netlist data. Additionally, we incorporate auxiliary and contrastive learning techniques to capture the differences across various PDNs. Extensive experiments on open-source designs demonstrate the superior performance of our model.
Fast and Effective Logic Gate Sizing Based on Heterogeneous Graph Neural Network
Presenter: Yuhan Dong, Southeast University
Abstract: Gate sizing serves as a fundamental netlist optimization technique for enhancing performance and power in the physical design flow. Traditional heuristic sizing algorithms prove computationally expensive, while existing machine learning approaches do not fully capture the influence of neighboring instances. In this work, we present a fast and effective end-to-end algorithm for post-placement logic gate sizing. It combines recursive feature elimination, a heterogeneous graph neural network encoder, and function-specific prediction heads to capture multiscale graph information and learn high-quality instance representations, delivering accurate sizing solutions. Experimental results on ICCAD 2024 Contest benchmarks demonstrate that our method eliminates 98.6% of negative slacks, along with 99.2% of slew and load violations, achieving 12.86x acceleration over median contestant runtime. In terms of the contest evaluation metric, which balances performance gains, power savings, and computational efficiency, our approach secured third place in the contest.
A Configurable Piecewise-Linear Approximation Squarer with Unbiased Error Compensation for Energy-Efficient Floating-Point Computing
Presenter: Wenjing Huang, Zhejiang University
Abstract: Approximate computing has emerged as a promising paradigm to enhance energy efficiency in applications where strict computational accuracy is not essential. In this work, we propose PAS, a piecewise-linear approximate floating-point squarer with unbiased error compensation and runtime configurability. PAS employs linear interpolation to iteratively approximate the square function, achieving configurability through multi-level error compensation. To optimize per formance, we design a multi-level, parallelizable circuit architecture that relies solely on negation and shifting operations, significantly reducing hardware complexity. Additionally, we introduce a runtime-configurable tree structure that dynamically adapts to varying precision requirements, making PAS highly versatile for diverse application scenarios. Compared to state-of-the-art approximate squarers and multipliers, PAS achieves a superior balance between accuracy and resource efficiency. Experi mental results demonstrate that PAS significantly reduces errors, with improvements of over 30% in MAE and 53% in MSE compared to existing designs, while also reducing area-delay product (ADP) by 13-42%. Application-level evaluations, such as in square-law demodulation (SLD), further validate PAS's effectiveness, showing that it achieves the best signal-to-noise ratio (SNR) and Euclidean distance performance, even when compared to exact squarers. These results highlight PAS as a highly efficient and adaptable solution for energy-constrained applications requiring approximate squaring operations.
A Statistical Static Timing Analysis Algorithm Based On Graph Neural Network