EDA² | ISEDA 2025 | Technical Session

Routing, Interconnect, and Partitioning Innovations

Abstract: Macro placement (MP) is essential in designing very large-scale integrated (VLSI) circuits. However, existing MP approaches face two main challenges: the adaptability to different objectives and the consideration of potential impacts on subsequent workflows. To overcome these challenges, an intuitive approach is to refine the placements generated by existing placers, known as macro placement refinement. This paper introduces a novel multi-mask driven evolutionary algorithm framework, MAD-EA, for intelligent adaptive MP refinement. MAD-EA can be seamlessly integrated as a plugin with any placer to refine initial placements. It incorporates diverse metrics such as dataflow, half-perimeter wire length (HPWL), and regularity, aligning with post-MP workflow metrics to enhance power, performance, and area (PPA). To effectively optimize these diverse objectives simultaneously, MAD-EA employs a multi-mask strategy with the Dataflow Mask, HPWL Mask, and Regularity Mask to optimize dataflow, HPWL, and congestion. Experiments show that MAD-EA improves HPWL by up to 33.00\% and congestion by 22.74\% compared to the state-of-the-art methods.

Abstract: Global placement is a critical step in modern VLSI physical design. Traditional electrostatic-based analytical placement algorithms, such as ePlace, employ a two-layer optimization loop: an inner loop using Nesterov's gradient descent, and an outer loop updating the density penalty multiplier to progressively enhance the density penalty. However, these conventional update methods often fail to balance the optimization efforts across different nets, leading to suboptimal solutions. In this paper, we introduce an adaptive preconditioning algorithm that addresses these limitations. Our approach utilizes divergence analysis to identify clusters within the placement region, followed by net preconditioning to adjust the optimization efforts accordingly. This ensures a more balanced distribution of optimization efforts across all nets, leading to improved placement quality. Experimental results on the DAC-2012 benchmarks suite demonstrate that our algorithm achieves a reduction in final placement wirelength compared to DREAMPlace, while obtaining an optimal tradeoff between half-perimeter wirelength (HPWL) and iteration count.

Abstract: With the expansion of design scales, the surge of adjustable parameters for electronic design automation (EDA) tools makes manually tuning parameters become time-consuming and challenging.Recent works employ multi-objective Bayesian optimization (BO) for automatic parameter tuning. However, non-deterministic design results of EDA tools undermine the effectiveness of BO. The existing forking technique, which can obtain reliable results by conducting design in parallel with identical parameter inputs, requires extracomputational resources and runtime. To address results nondeterminism under multithreading mode, our proposed BO framwork employs an oisyex pected hypervolume improvement (NEHVI) acquisition function to conduct parameter tuning. Experimental results demonstrate that our framework achieves superior optimization results with faster convergence compared to state-of-the-artworks.

Abstract: Differentiable optimization is popular for its efficiency and explainability. However, it faces limitations due to its reliance on continuous formulations and constraints on objective expressivity. To address these challenges, we propose a framework combining differentiable methods with gradient clipping and calibration strategies to ensure efficient and targeted optimization. Gate sizing, a key challenge in chip PPA optimization, exemplifies all the challenges with its discrete nature and objective complexity. Applying our proposed differentiable framework to gate sizing, we outperform top contestants in the 2024 ICCAD CAD gate sizing contest in overall quality scores and runtime, with excellent and balanced performance on all important evaluation metrics.

Abstract: As modern System-on-Chip (SoC) designs incorporate an increasing number of heterogeneous macros, an effective RTL-aware macro placement method becomes crucial for optimizing design performance. This paper presents HDPlacer, a novel macro placement framework that incorporates design hierarchy and dataflow connectivity to improve placement quality. We first construct a hierarchy tree and introduce a hierarchy-aware clustering method to effectively extract logical information and dataflow dependencies. Then, we employ a dataflow-aware analytical approach to determine the initial placement of clusters and a simulated annealing (SA)-based optimization to assign preferred regions for clusters. Finally, we develop a comprehensive analytical-based global placement with dataflow-aware net weighting and differentiable region guidance formulation, in which nets are systematically classified and assigned adaptive weights to enhance modularity and minimize critical path delays. Experimental results on ICCAD 2015 contest benchmarks demonstrate that HDPlacer achieves superior placement quality compared to the state-of-the-art placers RePlAce and Hier-RTLMP.