Advanced Analog Simulation and Verification Techniques
Session Chair: Xuanqi Chen, Huawei Design Automation Lab, Hong Kong
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design
Presenter: Weiyu Chen, National Center of Technology Innovation for EDA
Abstract: Recent advancements have demonstrated the significant potential of large language models (LLMs) in analog circuit design. Nevertheless, testbench construction for analog circuits remains manual, creating a critical bottleneck in achieving fully automated design processes. Particularly when replicating circuit designs from academic papers, manual Testbench construction demands time-intensive implementation and frequent adjustments, which fails to address the dynamic diversity and flexibility requirements for automation. AnalogTester tackles automated analog design challenges through an LLM-powered pipeline: a) domain-knowledge integration, b) paper information extraction, c) simulation scheme synthesis, and d) testbench code generation with Tsinghua Electronic Design (TED). AnalogTester has demonstrated automated Testbench generation capabilities for three fundamental analog circuit types: operational amplifiers (op-amps), bandgap references (BGRs), and low-dropout regulators (LDOs), while maintaining a scalable framework for adaptation to broader circuit topologies. Furthermore, AnalogTester can generate circuit knowledge data and TED code corpus, establishing fundamental training datasets for LLM specialization in analog circuit design automation.
OSTC-FRVF: Order Determination and S-TSVD for Constrained Macromodeling of S Parameter
Dan Niu, Southeast University
Abstract: Macromodeling for S parameter, obtained by capturing the frequency response of multiport devices, is a crucial methodology for transient simulations. However, current methods face significant challenges in efficiency, reliability, and accuracy. FRVF will exceed the operational memory when applied to a circuit with 384 ports, and the error with an incorrect order is substantial. Algorithms like AAA and ORA may struggle to satisfy the conjugate properties and stability. To overcome these issues, this paper introduces OSTC-FRVF, a comprehensive solution that achieves acceleration, order correction, and constraint satisfaction. For accuracy, OSTC-FRVF establishes an order determination mechanism (O) to balance the relationship between accuracy and complexity. The improved peak detection method calculates the initial order, and Prony Analysis with a new termination condition adjusts the order promptly. For efficiency, to maximally utilize data redundancy to simplify the computational process, OSTC-FRVF designs a two-pronged acceleration method, S-TSVD. The innovative resonance sampling method (S) and the improved truncated singular value decomposition method (T) collaborate synergistically, which fully exploit the data characteristics to enhance the efficiency in macromodeling. For reliability, the constraints satisfaction method (C) addresses the DC preserve, D-passivity, conjugate properties, and stability to facilitate the success of transient simulations. The validity is thoroughly substantiated on circuits of diverse scales, spanning from 2 to 384 ports. OSTC-FRVF achieves an average speedup ratio of 25.69X and a maximum of 40.29X compared to FRVF. And the relative error is generally below 1%.
BPKSR: A Batch Parallel Krylov Subspace Recycling Method for Efficient Periodic Small-Signal Analysis in RF Circuit Simulation
Presenter: Lingyun Ouyang, Harbin Institute of Technology; Southern University of Science and Technology
Abstract: Periodic small-signal analysis in RF circuit simulations poses significant computational challenges, particularly when dealing with a large quantity of frequency points. Although Krylov subspace recycling and parallel computing are effective strategies for accelerating this process, their synergistic combination has remained unexplored. We propose BPKSR, a novel parallel multi-thread subspace recycling method specifically designed for periodic AC (PAC) and noise (PNoise) analysis. Initially, the frequency points are partitioned into multiple batches. For each batch, parallel processing of frequency points is carried out, leveraging the reuse of vectors in shared memory to minimize the number of iterations. Subsequently, a subspace is generated or augmented within each batch and then updated in the shared memory for recycling. Additionally, a frequency points allocation scheme is developed by jointly considering both the similarity between right-hand-side (RHS) vectors and the total number of threads, which aims to optimize parallel computational workloads.
Automated SAR ADC Sizing Using Analytical Equations
Presenter: Zhongyi Li, Ningbo Institute of Digital Twin
Abstract: Conventional analog and mixed-signal (AMS) circuit designs heavily rely on manual effort, which is time-consuming and labor-intensive. This paper presents a fully automated design methodology for Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) from performance specifications to complete transistor sizing. To tackle the high- dimensional sizing problem, we propose a dual optimization scheme. The system-level optimization iteratively partitions the overall requirements and analytically maps them to subcircuit design specifications, while local optimization loops determines the subcircuits' design parameters. The dependency graph-based framework serializes the simulations for verification, knowledge-based calculations, and transistor sizing optimization in topological order, which eliminates the need for human intervention. We demonstrate the effectiveness of the proposed methodology through two case studies with varying performance specifications, achieving high SNDR and low power consumption while meeting all the specified design constraints.
SMT-Based Analog Layout Retargeting: Multi-Mode Constraint Extraction and Weighted Optimization
Presenter: Jiwen Huang, Xiamen University
Abstract: In integrated circuit design, analog layout retargeting technology plays a key role in achieving design migration, optimizing layouts, and enhancing circuit performance. Existing methods face issues of inefficiency and limited flexibility in constraint extraction and layout optimization, especially in complex circuit designs where they struggle to intelligently differentiate between various types of constraints and balance optimization objectives. To address these challenges, this paper proposes an SMT-based layout migration method, which innovatively introduces multi-mode constraint extraction and distance thresholds to enhance the flexibility and accuracy of constraint extraction. Additionally, a weighted cost function is used to optimize the trade-off between area and interconnection length, providing flexibility to meet different design requirements. Experimental results show that this method significantly improves layout quality and solving efficiency in high-constraint-density scenarios.
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design
Presenter: Weiyu Chen, National Center of Technology Innovation for EDA