Abstract: The emergence of AI-driven intelligent computing has spurred an exponential increase in demand for compute power. At the same time, shifting geopolitical conditions and evolving supply chain dynamics are posing unprecedented challenges to the design and manufacturing of Chinese AI chips. In response, UniVista has introduced a comprehensive solution that integrates advanced EDA tools and high-performance IPs to enable software-driven and advanced-packaging–driven AI chip designs. In this talk, we will share UniVista’s latest innovations, including: (1) cutting-edge EDA tools, such as the UVHS emulator for system-level functional and performance verification, the Chiplet Explorer for advanced packaging design, and the UDA AI-powered digital design platform and (2) Advanced IP solutions, including RDMA, UCIe, and HBM. We will demonstrate how these technologies, working together, can help accelerate the design and innovation of Chinese AI chips to meet compute-power demands.
Electrothermal Simulation and Vertical Interconnect Planning for Integrated Chiplets
Presenter: Siyuan Miao, University of California, Los Angeles
Abstract: Chiplets are emerging as novel solutions for high-performance AI computing processors. Vertical interconnects (VICs) including μbumps, C4 bumps and through-silicon vias (TSVs) in chiplets are critical as they not only carry signals and power supplies but also transfer heat efficiently. Due to the need of fine-grained VIC modeling, existing thermal tools are ineffective for VIC-embedded chiplets. Moreover, electrothermal analysis in previous architectural simulators does not consider temperature dependence for short-circuit power, which is non-trivial in our experiments. To address the above problems, this paper proposes SYSgen, a framework for accurate, location-based temperature dependent power profiling and VIC planning for integrated chiplets. SYSgen achieves a 97.77× speedup with a maximum error below 1.2°C when the chiplet temperature is around 100°C compared to COMSOL. It also reduces VIC number by 21.7% and 12.4% compared to two existing papers with same constraints on signal and power routing and maximum temperature.
PHAROS: An Adaptive Optimization and DRC Correction Tool for Accurate Photonic Design Automation
Presenter: Qisheng Yang, Hunan University
Abstract: The rapid advancement of photonic computing has highlighted its potential for high-speed, low-power parallel computation. Nonetheless, traditional inverse design for photonic integrated circuits (PICs) face challenges, such as irregular structural patterns and the necessity for manual design rule checks (DRC). These factors contribute to extended design cycles and diminished efficiency. To address these problems, this work proposed PHAROS, an adaptive optimization tool for automated photonic design automation. PHAROS employs adjoint-method gradient optimization. It integrates adaptive filtering and quantization mechanisms. These features enable the simultaneous optimization of electromagnetic performance and adaptation to manufacturing constraints. Then, a feedback system further enabled automatic DRC correction, ensuring compliance with foundry-specific process design kits (PDKs). Simulation results demonstrated the PHAROS's robustness across diverse PDKs nodes and pixel resolutions. By automating the workflow from objectives to manufacturable layouts, PHAROS established a promising path for future optical design automation (PDA).
Domestic EDA Tools and IP Solutions: Accelerating Breakthroughs in Chinese AI Chip Design
Invited Speaker: Pei-Hsin Ho, Shanghai UniVista lndustrial Software Group Co., Ltd