EDA² | ISEDA 2025 | Technical Session

Advanced Test Methodologies and DFT Techniquesn

Session Chair: Huawei Li, Institute of Computing Technology, Chinese Academy of Sciences

Abstract: Safety-critical systems in automotive, air or space applications integrate the infrastructure for deterministic logic built-in self-test (DLBIST) to be used in the field periodically and at power-on and power-off. The BIST has to be effective for any admissible instance subject to process variations and under any admissible condition due to voltage and temperature fluctuations. This contribution discusses DLBIST solutions which optimize fault coverage, test storage requirements and test application times simultaneously.

Abstract: Modern integrated circuit (IC) development faces increasing demands for test coverage, cost efficiency, and reduced turnaround time, particularly with the shift to nanometer technology nodes and heterogeneous 3D integration. To address these challenges, we propose DFTS, a holistic Design-for-Test (DFT) methodology for scan design, consisting of five key components: netlist parsing, module uniquify operations, minimal MUX-based repairs of design rule checking (DRC) violations, balanced scanchain construction, and clean circuit dumping for automatic test pattern generation (ATPG) or fault simulation. DFTS employs hierarchical parsing to capture clock, set, and reset domains accurately while minimizing redundant module definitions through unique operations. A selective DRC-violation repair mechanism efficiently inserts MUXes only where necessary, avoiding overfixing in constant-gated or properly configured paths. Additionally, a multi-domain scan-chain balancing algorithm evenly distributes scan cells across clock domains; switching activities were shared over several clock domains, reducing shift cycles. Experiments on CPU-like netlists demonstrated significant reductions in unnecessary MUX insertions and a runtime speedup of 3×–43× compared to a leading commercial DFT solution. These results highlight the scalability and competitiveness of the proposed methodology, making it a robust solution for addressing DFT challenges in scan design of modern IC designs.

Abstract: Automatic Test Pattern Generation (ATPG) is a crucial technology in digital circuit testing. However, as circuit complexity increases, traditional methods face significant challenges, including inefficiency and resource waste caused by excessive backtracking. This paper presents an optimized ATPG method based on robust decision trees to mitigate backtracking and improve overall performance. The approach involves constructing a decision tree to learn the rich historical backtracking data generated during the FAN ATPG process, incorporating a negative exponential loss function to reduce the impact of noisy data on model quality. The trained model is then used to guide backtracking decisions in ATPG, thereby enhancing efficiency. Experimental results on ISCAS89 and ISCAS85 benchmark circuits demonstrate that, compared to deep learning-optimized ATPGmethods, the proposed approach reduces backtracking frequency by 24% and test pattern count by 25%, while maintaining comparable test quality.

Abstract: In modern machine learning models like Transformers, matrix multiplication dominates most computation. Specific hardware often uses large-scale PE arrays, such as systolic arrays, to accelerate this process. However, these extensive PE arrays tend to experience high fault rates, with cumulative errors in matrix multiplication potentially impacting final algorithmic outcomes. We propose GEMMHeal, a self-repairing, systolic-array-like architecture optimized for matrix multiplication. This architecture optimizes the matrix multiplication array design and data flow in the buffer while decoupling the error correction (EC) core from the array. The EC core operates as an independent computation unit, maintaining resource efficiency and avoiding performance degradation due to the spatial locality of faults. Additionally, our proposed design incorporates redundancy within the EC core, allowing it to self-repair and thus further improve fault tolerance. GEMMHeal is implemented in a 32nm process to demonstrate its area and physical achievability. A single EC core occupies only 1.8% of the area while effectively repairing up to 6.3% of faulty PEs, all while maintaining overall performance. By accounting for potential faults within the EC core, our redundant design achieves an average improvement of 31% in the EC core normal rate compared to non-redundant designs when the computation cell fault rate is within 15%.