EDA² | ISEDA 2025 | Technical Session

Power Modeling, Analysis, and Thermal Management

Abstract: With the increasing complexity of functionality and scale in network processing and AI chips, power has become a critical constraint in the design of future processor architectures. Therefore, accurately quantifying processor power during the early stages of design and at higher levels of abstraction is crucial. Particularly in scenarios such as network packet switching, where time-series feature dependencies are significant, fully exploiting and utilizing temporal correlations can significantly enhance power prediction performance. This article proposes an ESL power prediction model that extracts key features from ESL model simulations and architectural design parameters, combined with a Long Short-Term Memory (LSTM) to construct an architecture-level power prediction model. Validation was performed on high-throughput network switching chips. The results show that the proposed model effectively improves the accuracy of ESL power prediction, achieving an average prediction error of less than 5% for both component-level and system-level power, with the best case reaching as low as 1.8%.

Abstract: Thermal analysis is crucial for modern chip design. The Path Integral Random Walk (PIRW) solver is a high-precision and highly parallel stochastic method-based solver, which is accurate for steady-state thermal analysis with mixed boundary conditions. However, it requires a large number of paths to ensure a result with small variance, as well as massive jump steps to ensure the convergence of the accumulated temperature. This results in limited performance when executed on CPUs. To address these limitations, we have developed a GPU-accelerated implementation of PIRW that capitalizes on the massive parallelism and advanced scheduling capabilities of modern GPUs. Our implementation enables large-scale parallel computation of random walk paths, significantly enhancing computational efficiency. Furthermore, by leveraging the algorithm's inherent characteristics, we have developed a fitting algorithm that substantially reduces the number of path steps required for convergence. The experiment shows that, compared to multi-threaded version on CPU with 80 threads, the PIRW on NVIDIA A800 GPU with step-reducing fitting technology achieves a speed up of 64.1x.

Abstract: On-chip temperature monitoring is becoming increasingly significant in preventing local over-heating and managing the reliability of electronic system, especially in 3D-stacked chips. A cost-effective thermal sensor planning method that assists in accurate temperature tracking in different application scenarios is highly desired. Therefore, we propose a mutual information (MI)-based technique to allocate the limited thermal sensors while maintaining a high level of accuracy in full thermal maps (resolution: <1 K). The thermal analysis workflow to assist in the hotspots monitoring from the standard cell level down to the device level is presented, aiming at effectively capturing the time-varying and scenario-dependent thermal responses with finer granularity. The results suggest that the proposed method exhibits lower errors compared to existing approaches that use the same number of thermal sensors, and also shows great robustness in unknown scenarios.

Abstract: Power side-channels can cause leakage of cryptographic keys and pose a significant threat to hardware security. Although post-silicon power side-channel analysis methods are generally effective in leakage assessment, discovering side-channels after fabrication is too late, since security vulnerabilities in chips are difficult to eliminate or patch. This work aims to develop a pre-silicon power side-channel leakage assessment method that allows the evaluation of power leakage in the early hardware design and verification stages through quantitative information flow analysis. The key observation is that the distribution of taint labels can reveal power consumption characteristics. The paper constructs fine-grained precise information flow models (IFM) for cryptographic hardware designs for calculating taint labels. It further employs Shannon entropy to measure the distribution of taint labels related to secret key bits and quantify power side-channel leakage. Experimental results using AES and SM4 core designs show that our method can precisely identify modules with power side-channel security vulnerabilities and quantitatively assess the degree of leakage.