EDA² | ISEDA 2025 | Technical Session

AI-Driven Design Automation and Open Source Initiatives

Abstract: The increasing demand for flexible module integration necessitates the placement of rectilinear soft modules, which pose significant challenges in floorplanning, particularly under fixed-outline constraints and with pre-placed modules. In this paper, we propose an effective fixed-outline floorplanning algorithm for rectilinear soft modules. We first present electrostatics-based global floorplanning with a module-area-growing strategy to optimize the positions and dimensions of soft modules. Then, a negotiation-based legalization method is proposed to eliminate overlaps between modules, where a polygonal shape determination method for rectilinear soft modules is presented to minimize wirelength while considering polygonal shape constraints. Finally, a polygon-clipping-based refinement method is developed to further optimize both shape and wirelength. Based on the GSRC and MCNC benchmarks, experimental results demonstrate that our algorithm achieves a smaller half-perimeter wirelength (HPWL) in a reasonable runtime.

Abstract: Analog topology synthesis is one of the major challenges in analog design automation since the topology of analog circuits has a large design space and contains a lot of human expertise. Traditional methods suffer in generating high-quality topology due to the diversity of topologies and the lack of ability to understand human experience. Therefore, LLM has been adopted in recent studies to generate such topologies. However, most of the existing work utilizes ideal modelbased generation or ambiguous design requirements, both of which are not in line with industrial practice and require additional effort. In this work, we propose AnalogXpert, an LLM-based agent formulating topology synthesis as subcircuit-level SPICE code generation which is more practical. AnalogXpert incorporates circuit design expertise by introducing a proofreading strategy that allows LLMs to incrementally correct the errors in the initial design. Finally, we construct a highquality benchmark validated by both real data (30) and synthetic data (2k). AnalogXpert achieves 40% and 23% success rates on the synthetic dataset and real dataset respectively, which is markedly better than those of GPT-4o (3%,3%) and AnalogCoder (8%,6%).

Abstract: We introduce ForgeEDA, an open-source comprehensive circuit dataset across various categories. ForgeEDA includes diverse circuit representations such as Register Transfer Level (RTL) code, Post-mapping (PM) netlists, And-Inverter Graphs (AIGs), and placed netlists, enabling comprehensive analysis and development. We demonstrate ForgeEDA's utility by benchmarking state-of-the-art EDA algorithms on critical tasks such as Power, Performance, and Area (PPA) optimization, highlighting its ability to expose performance gaps and drive advancements. Additionally, ForgeEDA's scale and diversity facilitate the training of AI models for EDA tasks, demonstrating its potential to improve model performance and generalization. By addressing limitations in existing datasets, ForgeEDA aims to catalyze breakthroughs in modern IC design and support the next generation of innovations in EDA.

Abstract: This paper presents Spec2Doc2RTL, a hierarchical LLM-based RTL code generation framework leveraging natural language as the intermediate design representation. To address the complexity of design hierarchies and circuit diversity, we propose a universal recursive decomposition method that transforms the circuit design process into the nested module implementations. We introduce a register-transfer-level (RTL) code generation pipeline from design specifications based on natural language representation, which includes two LLM-friendly stages: design document generation (Spec2Doc) and document-to-RTL translation (Doc2RTL). Moreover, a fully automated iterative design workflow is implemented, with script generation, testing, and debugging integrated. Experimental results demonstrate that Spec2Doc2RTL can generate a wide spectrum of circuits, from complex systems like CPUs and NTTs to foundational bottom-level modules with a competitive 78.8% accuracy on the Revisiting VerilogEval benchmark.

Abstract: As the size of chips continues to shrink, the optical proximity effect becomes increasingly pronounced. Lithography hotspots, such as open circuits or short circuits, may manifest during the manufacturing process, adversely impacting chip yield and reliability. Although deep learning has been widely applied to hotspot detection, challenges remain in achieving high recall and precision. In this paper, we propose a hotspot classification model MF-VIT based on an improved Vision Transformer, addressing these challenges using a multi-scale feature fusion strategy. In addition, the Focal Loss function is introduced to effectively mitigate the issue of imbalanced lithography hotspot data. Comparative experiments on the ICCAD-2012 Contest benchmarks demonstrate that the proposed method achieves superior classification performance, yielding an overall average recall rate of 98.5%.