EDA² | ISEDA 2025 | Technical Session

Reliability Engineering and Post-Layout Optimization

Abstract: In today’s semiconductor industry, the pressure to innovate at ever-shrinking nodes while maintaining high yields has never been greater. Traditional design methods often struggle to address the increasing complexity of process variations, limiting both performance and manufacturability. This is where Pattern-Driven solutions come in—offering a smarter, more adaptive approach to semiconductor design.
At Semitronix, we’ve developed a cutting-edge Pattern-Driven solution that seamlessly integrates with existing workflows to optimize design layouts, ensure manufacturability, and significantly reduce time-to-market. By leveraging advanced machine learning and key simulations, our solution anticipates potential manufacturing issues early, providing real-time, actionable insights.
With proven success in high-density applications, our solution not only improves yield but also enhances design-to-manufacturing alignment, resulting in lower costs and better performance. Our roadmap further expands on these capabilities, introducing next-gen optimizations and AI-driven advancements to meet the evolving needs of the semiconductor industry.
Join us as we explore how Pattern-Driven technology is poised to transform the way we design and manufacture the next generation of semiconductors.

Abstract: Digital circuit reliability is increasingly challenged by aging effects, particularly Bias Temperature Instability (BTI), which gradually shifts threshold voltages, degrades key electrical parameters, and exacerbates timing violations. To address these challenges, this paper proposes a systematic and efficient methodology for digital circuit aging assessment which is fully compatible with existing design flows. Our approach introduces a two-tiered framework that first derives cell-level signal probabilities (SP) from circuit-level analysis, and then leverages cell-level SPs to evaluate device-level BTI per cell. By utilizing an accelerated algorithm that derives cell-level SP directly from the synthesized netlist, our method eliminates dependence on simulation tools, thereby reducing the overall run-time and greatly improving the efficiency of aging assessment. Through a graph-based algorithm, device BTI per cell is determined and this process is integrated into the aging library characterization flow. Furthermore, our iterative technique for sequential cells efficiently resolves SP calculation problems of feedback loops, allowing accurate SP calculation throughout the entire design. Experimental results on the ISCAS85 and EPFL benchmarks demonstrate an average runtime speedup of 18.44× while verifying the correctness of the proposed method on simple benchmark circuits. Moreover, the runtime advantage becomes even more pronounced for larger-scale circuits.

Abstract: With the advancement of technology, process variations have a critical impact on key IC designs. Accurately and efficiently estimating circuit failure rates under process variations has become increasingly challenging due to the "curse of dimensionality" introduced by a large number of random variables. Traditional Monte Carlo methods incur prohibitively high computational costs. In this paper, we propose a meta-modeling approach that integrates polynomial chaos expansion(PCE) with low-rank tensor approximation to effectively address these challenges. This method mitigates the "curse of dimensionality", ensuring that computational cost scales linearly with dimensionality. Specifically, we employ tensor train (TT) decomposition to achieve a low-rank approximation of the original tensor, demonstrating superior performance in SRAM column circuit simulations. Compared to CANDECOMP/PARAFAC(CP) decomposition, the TT-based approximation offers greater accuracy and stability. Additionally, we incorporate sensitivity analysis to further reduce computational costs.

Abstract: With the advancement of integrated circuit technology nodes, distortion occurs in pattern transfer inevitably caused by Optical Proximity Effect (OPE). Model-based OPC (MB-OPC) is the most commonly used solution in the industry. MB-OPC relies on an accurate lithography model to guide it. However, numerous challenges are in face when tuning a lithography model. Scanning Electronic Microscope (SEM) images—the most critical data for lithography model tend to be noisy. The current method of image denoising is frame averaging, but it’s time-consuming and affected by resist shrinkage, leading to inaccuracy model. Deep learning methods in previous study lack real and accurate SEM images. We collected reliable SEM images from a fab by overlying Multi die single frame images, and a UNet-based GAN model is designed for denoising. Experiment demonstrates that MSE, PSNR, and SSIM of our methods are at least 9.1%, 2.7% and 1.4% better than other methods. Moreover, our method outperforms other methods in preserving process metrics like line widths and contour accuracy, closely approximating the target images.

Abstract: With the rapid advancement of semiconductor technology and the continuous miniaturization of circuit feature sizes, hotspot detection has become an increasingly critical yet challenging task in physical verification workflows. In recent years, numerous deep learning frameworks have been developed to address hotspot detection. However, the performance of these learning-based frameworks is heavily dependent on the quality of the datasets used. However, obtaining a large labeled hotspot dataset with high quality is an extremely time-consuming process. Recently, masked image modeling (MIM) has drawn significant attention for its ability to learn from vast amounts of unlabeled data and has demonstrated effectiveness across a wide range of image tasks. Despite its success, the application of MIM to layout analysis, particularly in the context of semiconductor design, remains largely unexplored. Motivated by the principles of MIM, we propose a transfer learning framework that leverages pretraining through masked layout modeling (MLAM) and subsequently fine-tunes the model on limited labeled hotspot detection datasets. Experimental results on our custom layout datasets demonstrate the effectiveness of our approach.