Physical Design and 3D/2.5D Integration Techniques
Session Chair: Thai Nguyan, Intel Corporation
EDA for Chiplet Planning, Design and Verification
Invited Speaker: Chen Wu, Ningbo Institute of Digital Twin, Eastern Institute of Technology
Abstract: Chiplets, as a critical technological pathway in the post-Moore era, enable continuous expansion of functionality and performance through heterogeneous integration of multiple chips. However, it is still challenging for current chiplet design methodologies and tools. Automation Challenges: Existing EDA tools (both domestic and international) suffer from low routability, requiring extensive manual intervention. There is an urgent need for automated design tools for system generation, physical planning, placement, and routing. Multi-Physics Simulation Bottlenecks: Conventional field-solver-based multi-physics simulation tools often require layout truncation, leading to excessively long simulation times and incompatibility with incomplete designs. Rapid analysis algorithms for signal integrity (SI), power integrity (PI), electrothermal coupling, and other multi-physics effects are urgently needed. Design-Verification Disconnect: Current fragmented workflows between design and verification tools result in lengthy iterative cycles (design-verify-redesign), sometimes even failing to converge. A "shift-left" design verification process is imperative to reduce iteration overhead. This talk addresses the above pain points by presenting a comprehensive workflow for chiplet physical design and verification. Physical Planning: We introduce methodologies for physical planning that prioritize thermal management, power delivery, and routing feasibility (considering SI/PI constraints). AI-Driven Multi-Physics Evaluation: We propose a data-driven and AI-accelerated multi-physics evaluation model to rapidly predict and optimize performance metrics across electrical, thermal, and mechanical domains.Convergent Design Flow: By integrating the proposed models, we demonstrate a unified design-verification framework that adopts a "shift-left" approach, enabling early-stage validation and significantly reducing iterative cycles.
Leveraging Steiner Tree Grid Segment in GNN for VLSI Pre-Routing Congestion Prediction
Presenter: Xuan Peng, South China University of Technology
Abstract: Congestion problem is the most critical issue that the very large scale integration (VLSI) industry has to face during physical design. Modern placement and routing tools often optimize performance based on congestion conditions. An accurate congestion prediction model can effectively enhance the quality of placement and routing to effectively reduce the number of time-consuming and computationally-intensive iterations. In this paper, based on the Steiner Tree graph structure, we design a new graph node, GSegment, and propose a Graph Neural Network-based model, STGSG, for binary classification of the routing overflow congestion. Experimental results on real-world designs demonstrate that, compared to the model without using GSegment, our model has an approximately 23\% improvement in the F1 score. The experiments proved the key influence of the routing probability calculation based on GSegment on the classification performance. Our dataset and code can be obtained at https://github.com/pxgh02/STGSG.
RepPart: An Efficient Partitioning Framework with Replication Technique for MFS
Presenter: Haonan Wu, Xidian University
Abstract: The design of large-scale digital integrated circuits (ICs) increasingly relies on logic verification, with FPGA-based hardware emulation emerging as a critical component. Efficient partitioning of the circuit netlist and its mapping to a multiFPGA system (MFS) for emulation has become a key research focus. Due to limited I/O resources, each FPGA is typically connected directly to only a few other FPGAs. Consequently, signal transmission must pass through intermediate FPGAs, which act as hops in the signal path. This phenomenon increases signal delay and degrades overall system performance. This paper introduces RepPart, an efficient partitioning algorithm for multi-FPGA systems designed to simultaneously address multiple constraints. Building on multiple initial partitioning methods, the process is optimized by integrating the fast candidate partition propagation algorithm and the distant root node selection algorithm. Furthermore, solution quality is enhanced by replicating a limited number of critical nodes during the refinement process. Compared to existing approaches, RepPart achieves higherquality zero-hop solutions in significantly less time.
FLPlace: Macro Placement with Forward-Looking Wire Mask Guidance
Presenter: Caiyu Chen, Hangzhou Dianzi University
Abstract: The development of Very Large Scale Integration (VLSI) technology has introduced new challenges for Electronic Design Automation (EDA) in chip placement. Macro placement is a crucial subproblem in the placement process, focused on determining the positions of all macros to minimize half-perimeter wire length (HPWL) while avoiding overlaps. Recently, wire-mask-guided macro placement methods have shown the potential to achieve promising results for macro placement. However, these methods are prone to getting stuck in local optima, as they focus solely on selecting the current optimal position for placing a macro. In this paper, we proposed a wire-mask-guided macro placement method called FLPlace. Firstly, we presented a forward-looking wire-mask-guided algorithm that accounts for the impact of the current macro’s position on subsequent macros, thus optimizing the overall layout. Secondly, we introduced a heuristic space exploration strategy to enhance optimization efficiency. Experimental results on the ISPD2005 and ariane benchmark demonstrate that FLPlace outperforms the wire-mask-guided method WireMask-BBO, achieving an 11.71% optimization in HPWL and converging to a high-quality solution more rapidly.
OASALT: On the Construction of Obstacle-Avoiding Steiner shAllow-Light Tree
Presenter: Wing Ho LAU, The Chinese University of Hong Kong
Abstract: In routing tree generation, two important metrics are introduced to evaluate the quality. Wirelength (WL) is directly related to power consumption, routing resource usage and wire delay while pathlength (PL) is indicative of the wire delay. SALT and PD-II are the leading algorithms for the construction of shallow-light routing trees. However, they cannot handle the real designs with blockages. In this paper, we extended the SALT to be Obstacle-Avoiding Steiner shAllow-Light Tree (OASALT) to handle obstacles. First, we improve the time complexity of Lin's Obstacle-Avoiding Spanning Graph (OASG) from O(n^2 logn) to O(n^2). In addition, we extended the CL algorithm to generate Obstacle-Avoiding Rectilinear Steiner Minimum Arborescence (OARSMA). The experiment shows that OASALT can achieve a better tradeoff between WL and PL under the cases with obstacles, by combining Obstacle-Avoiding Rectilinear Steiner Minimum Tree (OARSMT) and OARSMA. Compared to performance-driven Obstacle-Avoiding Rectilinear Steiner Tree (PDOARST), OASALT improves the worst delay by 15% and WL by 10% on average.
EDA for Chiplet Planning, Design and Verification
Invited Speaker: Chen Wu, Ningbo Institute of Digital Twin, Eastern Institute of Technology