EDA² | ISEDA 2025 | Technical Session

Analog/Mixed-Signal Synthesis and Layout Optimization

Abstract: The continuous expansion of the scale of analog circuits poses significant challenges to the automation of circuit design. This is mainly reflected in the longer simulation time and insufficient exploration of the design space. Traditional optimization algorithms focus on finding optimal points, often overlooking the simulation cost. In this work, we frame the original problem as a multi-armed bandit problem. By applying a Thompson sampling strategy, we achieve a balance between global exploration and local exploitation. During the local exploitation, we propose a sensitivity-guided method ensuring rapid convergence. Experimental results demonstrate that our approach outperforms state-of-the-art techniques, achieving a 5.27x speedup and better global exploratory capabilities.

Abstract: Analog circuit design is traditionally dependent on extensive human expertise, making the process time consuming and labor intensive. This paper introduces LLMACD, a knowledge-embedded automation designer for analog circuit design based on large language models (LLMs). We design a refined prompt manager to extract circuit representation, embed circuit knowledge, and model the knowledge-intensive design process within a Chain-of-Thought (CoT) workflow. Leveraging LLMs' in-context learning capabilities and high-quality humanannotated design experience, LLMACD derives transistor behavioral parameters by analyzing performance expressions in a human-like manner without complex iterative loops, thereby accelerating the design process. Experimental results demonstrate that LLMACD outperforms traditional iterative transistor sizing optimization methods, achieving faster design times and enhanced circuit performance, with performance gains of up to 2 times.

Abstract: Automatic transistor sizing in circuit design remains a significant challenge. While Bayesian optimization (BO) has shown promise, its optimization process is hindered by large design spaces for most practical circuits, particularly as technology nodes shrink. Inspired by professional analog circuit design workflows where key factors are identified and prioritized in optimization, we propose Design Space Folding (DSFold) to imitate such a process to assist design convergence. The optimization is initially conducted in a folded design space, allowing design points to escape saddle points and converge quickly toward potential global optima, with the design space progressively unfolding to consider all variables. We assess DSFold by equipping it with many stateof-the-art (SOTA) transistor sizing optimizers on multiple analog circuit benchmarks and show a 1.05x-5.34x speedup and a 1.10x-2.91x convergence performance improvement compared to their original forms with almost zero extra cost (only ∼3% computational overhead), achieving significant improvements while maintaining the “free-lunch” advantage.

Abstract: Transient simulation is a major computational bottleneck in analog circuit sizing optimization, especially when the circuit is unstable. Simulation-based methods achieve high accuracy but suffer from inefficiency, while surrogate-based approaches promise speedups but struggle with prediction errors and high computational costs. Challenges like poor transferability and reliability constrain their efficacy in accelerating the circuit sizing process. In this paper, we propose an optimization strategy with a transferable pole-zero-based transient assertion (PZTA) system. Inspired by transient analysis theory, the PZTA system is applicable across different topologies and effectively prunes unnecessary simulations with high accuracy. We design an offline-trained neural network model that incorporates circuit theory-inspired features, accurately asserting inferior circuit transient behavior in a zero-shot manner and adaptable to multiple optimization algorithms. Experimental results demonstrate that PZTA system effectively transfers across topologies and prunes over 83.87% of transient simulations exhibiting unstable behavior or inferior performance, with less than 1% false alarms. Our optimizers PZTA-M and PZTA-G on average reduce runtime by 49.54%.

Abstract: In the design process of the analog circuit pre-layout phase, device sizing is an important step in determining whether an analog circuit can meet the required performance metrics. Many existing techniques extract the circuit sizing task as a mathematical optimization problem to solve and continuously improve the optimization efficiency from a mathematical perspective. But they ignore the automatic introduction of prior knowledge, fail to achieve effective pruning of the search space, which thereby leads to a considerable compression margin remaining in the search space. To alleviate this problem, we propose a large language model (LLM)-based multi-agent framework for analog circuits' sizing relationships extraction from academic papers. The search space in the sizing process can be effectively pruned based on the sizing relationship extracted by this framework. Eventually, we conducted tests on 3 types of circuits, and the optimization efficiency was improved by 2.32 ~ 26.6 \times. This work demonstrates that the LLM can effectively prune the search space for analog circuit sizing, providing a new solution for the combination of LLMs and conventional analog circuit design automation methods.