EDA² | ISEDA 2025 | Technical Session

Large Language Models and Next-Generation EDA Tools

Abstract: This presentation will discuss some potential EDA fields in which AI can help improving efficiency and accuracy such as modeling, classifying, prediction etc. Then it will introduce latest progress of Empyrean's one stop agile full-custom IC design platform using AI assisting circuits generation and migration.

Abstract: Large Language Model (LLM) exhibits great potential in designing of analog integrated circuits (IC) because of its excellence in abstraction and generalization for knowledge. However, further development of LLM-based analog ICs heavily relies on textual description of analog ICs, while existing analog ICs are mostly illustrated in image-based circuit diagrams rather than text-based netlists. Converting circuit diagrams to netlists help LLMs to enrich the knowledge of analog IC. Nevertheless, previously proposed conversion frameworks face challenges in further application because of limited support of image styles and circuit elements. Up to now, it still remains a challenging task to effectively convert complex circuit diagrams into netlists. To this end, this paper constructs and opensources a new dataset with rich styles of circuit diagrams as well as balanced distribution of simple and complex analog ICs. And a hybrid framework, named Image2Net, is proposed for practical conversion from circuit diagrams to netlists. The netlist edit distance (NED) is also introduced to precisely assess the difference between the converted netlists and ground truth. Based on our benchmark, Image2Net achieves 80.77% successful rate, which is 34.62%-45.19% higher than previous works. Specifically, the proposed work shows 0.116 averaged NED, which is 62.1%-69.6% lower than state-of-the-arts.

Abstract: While many EDA tools now incorporate machine learning, and data-driven approaches from AI-assisted EDA (AI4EDA) prediction techniques shift the design process left, researchers require increasingly larger datasets to ensure model generalization. However, the scarcity of open-source IP designs, the insufficiency of open-source AI4EDA datasets, and lengthy tool runtimes contribute to the high time, economic, and effort costs of obtaining sufficient data. To address these challenges, we propose a Sketch-to-Style layout image generation framework, which rapidly produces high-quality yet meaningful layout images from limited data. To demonstrate its effectiveness, we focus on generating Design Rule Violation (DRV) feature maps, serving as an augmentation method for DRV prediction—an AI4EDA innovation. Our experiments show that integrating "fake" data from the proposed framework with real datasets steadily improves the performance of Structure Similarity Index Measure (SSIM), while improving 5.11% of the Area Under the Curve of the Receiver Operating Characteristic (AUC of ROC), 32.27% of accuracy and reducing 19.28% of False Positive Rate (FPR) in imbalanced category predictions at the same time, enhancing the model's ability to learn DRV structural features and localization patterns. The proposed framework show great potential of generating image data for various prediction tasks.

Abstract: With the rapid advancement of electronic information technology, data security has become increasingly critical. While hybrid encryption provides higher security compared to traditional single encryption methods, its computational complexity leads to significantly higher resource consumption, making it challenging to deploy in resource-constrained environments. To address this challenge, we propose a RISC-V based hybrid encryption coprocessor designed for the SM2 and SM4 algorithms, achieving an efficient balance between resource utilization and performance. Through custom instruction set design and hardware/software co-optimization, the proposed coprocessor improves both resource efficiency and computational performance while enabling hybrid cryptographic operations. To validate the correctness and efficiency of the design, the coprocessor was integrated with the RISC-V processor and implemented on the Xilinx ZYNQ7020 FPGA. Experimental results show that, the proposed SM2 point multiplication operation achieves an 86.1% reduction in cycle count and a 28.5% decrease in resource consumption, while the SM4 implementation reduces hardware resource usage by 69.3%. These improvements highlight the effectiveness of the proposed design in enhancing the feasibility of hybrid encryption in resource-constrained environments.