EDA² | ISEDA 2025 | Technical Session

Emerging Technologies and Applications in EDA

Abstract: As conventional scaling comes to an end, 3D integration emerges as a compelling path forward, offering new dimensions in design flexibility, power efficiency, and density. For here, we present Flip FET (FFET), a new transistor architecture that leverages back-to-back stacking of transistors and interconnects on both sides of wafers, and introduce Flip 3D (F3D) integration, a novel 3D platform featuring dual-side integration. It enables symmetric, dual-sided standard cell design with aggressive cell height scaling down to 2.5 tracks, while maintaining excellent routability and performance.
Multiple innovations to address the complex vertical integration challenges will be addressed, with design techniques like multi-row placement, split gate, and dummy gate insertion also included. Furthermore, the novel dual-sided signal pins and routing capability unlock significant PPA benefits at the block level. Benefited from the dual-sided routing, further frequency gains and metal layer reductions can be achieved.
FFET and F3D not only represent a breakthrough in 3D device-circuit co-design but also provide a practical and manufacturing-friendly path to extend Moore’s Law from a design-centric perspective.

Abstract: Photonic inverse design has emerged as a transformative approach in the development of integrated photonic devices. The inverse design process primarily relies on two key steps: electromagnetic simulation and optimization algorithms. However, traditional numerical methods for EM simulation often face challenges such as computational inefficiencies, limited data utilization, and a lack of universality. Similarly, conventional iterative optimization algorithms used in inverse design suffer from high computational costs, susceptibility to local optima, and sensitivity to initial conditions. With the rapid advancements in artificial intelligence, machine learning offers a promising avenue to overcome these challenges, enabling efficient automated physical design of high-performance integrated photonic devices without the need for extensive photonics expertise. In this paper, we review several advanced methods that integrate ML into EM simulation and inverse design algorithms. Additionally, we emphasize the importance of incorporating manufacturing constraints to ensure the practical feasibility of the designed devices. By highlighting the potential of ML to revolutionize the design automation of integrated photonic devices, we aim to inspire further research and innovation in this field.

Abstract: Reconfigurable field-effect transistor (RFET) is a promising solution to break through the bottleneck of function density and energy efficiency for Post-Moore integrated circuits. This paper develops a Verilog-A implementable compact model for a ferroelectric-based reconfigurable field-effect transistor (Fe-RFET). The model captures the dynamic polarity switching of the Fe-RFET. In addition, novel logic cell circuits based on Fe-RFETs are proposed to achieve the multi-logic function with fewer transistors compared to conventional transistors based and double-gate transistors based cells, showing broad prospect of the application of our developed model.

Abstract: With the rapid advancement of electronic information technology, data security has become increasingly critical. While hybrid encryption provides higher security compared to traditional single encryption methods, its computational complexity leads to significantly higher resource consumption, making it challenging to deploy in resource-constrained environments. To address this challenge, we propose a RISC-V based hybrid encryption coprocessor designed for the SM2 and SM4 algorithms, achieving an efficient balance between resource utilization and performance. Through custom instruction set design and hardware/software co-optimization, the proposed coprocessor improves both resource efficiency and computational performance while enabling hybrid cryptographic operations. To validate the correctness and efficiency of the design, the coprocessor was integrated with the RISC-V processor and implemented on the Xilinx ZYNQ7020 FPGA. Experimental results show that, the proposed SM2 point multiplication operation achieves an 86.1% reduction in cycle count and a 28.5% decrease in resource consumption, while the SM4 implementation reduces hardware resource usage by 69.3%. These improvements highlight the effectiveness of the proposed design in enhancing the feasibility of hybrid encryption in resource-constrained environments.