EDA² | ISEDA 2025 | Technical Session

System-Level Simulation, Modeling, and Co-Verification

Abstract: In modern cyber-physical systems (CPS), multiple control applications typically share a common distributed computing platform, often spanning an edge-cloud continuum. This transition from dedicated, federated architectures to integrated platforms introduces complex timing behaviors, particularly variable and increased communication delays. These delays—arising from resource sharing and long-range 5G communications—can degrade control performance and, if left unmanaged, even destabilize the system. This talk presents a control/communication codesign framework that integrates delay compensation into both controller synthesis and task scheduling. The framework generates high-quality, stable CPS designs on distributed platforms. By explicitly accounting for the timing effects of shared computational and communication resources, this approach ensures robust and predictable control performance, even in highly dynamic environments.

Abstract: As the number of transistors on a processor chip grows, it takes a longer time to execute the simulation and iterate the architecture design. The performance of current processors is increasingly dependent on software and hardware cooperation. The network processor is a domain-specific processor widely used in routers and switches. Unlike general-purpose processors, network processors need to perform a lot of table lookup operations and execute microcode programs based on the table lookup results, which has a significant impact on chip performance. To speed up the simulation for network processors, we present a performance simulation methodology called codepath. It takes into account the characteristics of realistic network software and simulates the various behaviors of the packets reasonably at a certain abstract level. Compared to RTL (Register Transfer Level) simulation, it can speed up simulations by one or two orders of magnitude and the average simulation error of packet bandwidth is only 7.36%. The manpower investment can be reduced by 85% for the first version development.

Abstract: Digital in-memory computing (IMC) has drawn significant attention in neural network acceleration due to its superior energy efficiency and resistance to non-ideal variations. Simultaneously, the rapid evolution of neural networks and the large design space of IMC systems necessitate an early-stage verification simulator. In this paper, we introduce EFSim, an efficient and flexible simulation framework for digital in-memory computing systems. On the hardware level, a parameterized Chisel-based hardware library is constructed to enable the rapid and flexible generation of customized Verilog IMC circuits. On the software level, the IMC inference engine facilitates the efficient deployment of neural network models. Furthermore, EFSim performs hybrid compilation of designed IMC systems using Verilator, thereby enabling rapid performance evaluation and software–hardware co-optimization. Validation through two designed IMC macros demonstrates that the relative modeling error rate of EFSim is below 10%. Experimental results indicate that EFSim enables efficient evaluation of digital IMC systems and supports extensive design space exploration. The EFSim is open-sourced at https://github.com/cq-work/EFSim.

Abstract: With the rapid advancement of electronic information technology, data security has become increasingly critical. While hybrid encryption provides higher security compared to traditional single encryption methods, its computational complexity leads to significantly higher resource consumption, making it challenging to deploy in resource-constrained environments. To address this challenge, we propose a RISC-V based hybrid encryption coprocessor designed for the SM2 and SM4 algorithms, achieving an efficient balance between resource utilization and performance. Through custom instruction set design and hardware/software co-optimization, the proposed coprocessor improves both resource efficiency and computational performance while enabling hybrid cryptographic operations. To validate the correctness and efficiency of the design, the coprocessor was integrated with the RISC-V processor and implemented on the Xilinx ZYNQ7020 FPGA. Experimental results show that, the proposed SM2 point multiplication operation achieves an 86.1% reduction in cycle count and a 28.5% decrease in resource consumption, while the SM4 implementation reduces hardware resource usage by 69.3%. These improvements highlight the effectiveness of the proposed design in enhancing the feasibility of hybrid encryption in resource-constrained environments.